The present invention relates to phase detectors and in particular to sampling phase detectors.
Microwave and RF, Jul. 1993, pages 103 to 111, describes a hybrid circuit sampling phase detector. The detector includes a step recovery diode (SRD) and a sampling circuit. During a change of polarity at its terminals the diode conducts and supplies an impulse which constitutes a low-frequency reference to an input of a sampling circuit which also receives a high-frequency or radio-frequency signal to be sampled. The frequency of the signal to be sampled is N times higher than the frequency of the reference impulses, where N is an integer. The sampling circuit compares the impulse signal to the signal to be sampled. When the rising edge of the impulse reaches a level that is equal to the level of the signal to be sampled, a corresponding constant voltage level is supplied at the output of the sampling circuit. An output voltage proportional to the phase of the radio-frequency signal relative to a reference signal is therefore obtained. The sampling circuit includes a sampling transistor having a gate of intermediate width which represents a compromise between good phase sensitivity and a good DC output signal from the sampling circuit.
The above sampling phase detector has drawbacks. Firstly, the hybrid circuit implies a large overall size. Secondly, to generate adequate impulses, the SRD needs a high-power supply. These drawbacks are a particular handicap in aerospace applications. Also, this type of circuit requires many adjustments prior to use and its unit cost is high.
The document WO-A-99/18691 describes a totally digital phase comparator which indicates the phase between two clock signals. A radio-frequency analog signal is digitized and its digital approximation is compared to a digital model. The phase difference between the digital signals is then coded as a function of its amplitude in the form of a digital word.
Patent Abstract of Japan JP-0214009, xe2x80x9cSampling phase detectorxe2x80x9d, describes a sampling phase detector in the form of a monolithic integrated circuit which is produced on a Gaxe2x80x94As substrate and uses a field-effect transistor which is switched by amplitude limiting circuits, a delay circuit and an AND gate. Two signals are combined in a NOR gate to generate an impulse at a reference frequency.
The above sampling circuit has drawbacks. The field-effect transistor used has too low a resistance when it is turned off and too high a resistance when it is turned on. The phase sensitivity and stability of the output signal are therefore inadequate.
There is therefore a need for a sampling phase detector resolving one or more of the above drawbacks and there is also a need for a local oscillator including a phase detector as claimed herein.
The invention therefore proposes a sampling phase detector comprising a first sampling transistor having an input for a signal to be sampled at a frequency RF, an input for a control signal, an output for supplying a first sampled signal as a function of the phase between the signal to be sampled and the control signal, and a resistance between the input and the output when it is turned on less than (0.1xc3x9710xe2x88x9212xc3x97RF)xe2x88x921, and a second sampling transistor having a resistance between the input and the output when it is turned off greater than 100 ohms and having an input to which the first sampled signal is applied, an input for a control signal, and an output for a second sampled signal.
In an embodiment, the sampling transistors are field-effect transistors, the drain of the first transistor is the input for the signal to be sampled, the gate of the first transistor is the input for a control signal, the source of the first transistor is the output for the sampled signal, the drain of the second transistor is the input for the first sampled signal, the gate of the second transistor is the input for the control signal, the source of the second transistor is the output for the second sampled signal, and the resistance between the input and the output of the second transistor when it is turned off is greater than the resistance between the input and the output of the first transistor when it is turned off.
In an embodiment the source of the first transistor is shunted by a first capacitor and the source of the second transistor is shunted by a second capacitor.
In an embodiment the detector further comprises a control signal generator for supplying pulses to the inputs for control signals of the first and second transistors.
In an embodiment the control signal generator is implemented monolithically with the transistors.
The control signal generator can have an input for an AC reference signal and an inverter circuit for connecting the AC reference signal input to the input for a control signal of the first or second transistor.
In an embodiment the inverter circuit includes an SCFL gate.
In an embodiment the inverter circuit comprises three or four inverter stages.
In an embodiment the control signal generator supplies respective control signals in phase opposition to the first and second transistors.
The invention also provides a local oscillator including a phase detector as claimed herein.
The invention further provides a sampling phase detection method comprising the steps of providing a first sampling transistor having a resistance between its input and its output less than (0.1xc3x9710xe2x88x9212xc3x97RF)xe2x88x921 when it is turned on, providing a second sampling transistor having a resistance between its input and its output greater than 100 ohms when it is turned off, sampling the signal to be sampled in the first sampling transistor, and sampling the sampled signal in the second sampling transistor.
In an implementation the method further comprises the step of applying control pulses to the transistors to trigger the sampling steps.
In an implementation the control pulses are in phase opposition.
In an implementation the method further comprises a step of smoothing the sampled signals.